View ADA4930-1YCPZ-RL_2056921.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ultralow noise drivers for low voltage adcs ada4930-1/ada4930-2 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features low input voltage noise: 1.2 nv/hz low common-mode output: 0.9 v on single supply extremely low harmonic distortion ?104 dbc hd2 at 10 mhz ?79 dbc hd2 at 70 mhz ?73 dbc hd2 at 100 mhz ?101 dbc hd3 at 10 mhz ?82 dbc hd3 at 70 mhz ?75 dbc hd3 at 100 mhz high speed ?3 db bandwidth of 1.35 ghz, g = 1 slew rate: 3400 v/s, 25% to 75% 0.1 db gain flatness to 380 mhz fast overdrive recovery of 1.5 ns 0.5 mv typical offset voltage externally adjustable gain differential-to-differential or single-ended-to-differential operation adjustable output common-mode voltage single-supply operation: 3.3 v or 5 v applications adc drivers single-ended-to-differential converters if and baseband gain blocks differential buffers line drivers general description the ada4930-1/ada4930-2 are very low noise, low distortion, high speed differential amplifiers. they are an ideal choice for driving 1.8 v high performance adcs with resolutions up to 14 bits from dc to 70 mhz. the adjustable output common mode allows the ada4930-1/ada4930-2 to match the input of the adc. the internal common-mode feedback loop provides exceptional output balance, suppression of even-order harmonic distortion products, and dc level translation. with the ada4930-1/ada4930-2, differential gain configurations are easily realized with a simple external feedback network of four resistors determining the closed-loop gain of the amplifier. the ada4930-1/ada4930-2 are fabricated using analog devices, inc., proprietary silicon-germanium (sige), complementary bipolar process, enabling them to achieve very low levels of distortion with an input voltage noise of only 1.2 nv/hz. functional block diagrams 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 pd 10 +out 9v ocm 5 + v s 6 + v s 7 + v s 8 + v s 1 5 ? v s 1 6 ? v s 1 4 ? v s 1 3 ? v s ada4930-1 09209-001 figure 1. ada4930-2 1 ?in1 2 +fb1 3 +v s1 4 +v s1 5 ?fb2 6 +in2 15 ?v s2 16 ?v s2 17 v ocm1 18 +out1 14 pd2 13 ?out2 7 ? i n 2 8 + f b 2 9 + v s 2 1 1 v o c m 2 1 2 + o u t 2 1 0 + v s 2 2 1 ? v s 1 2 2 ? v s 1 2 3 ? f b 1 2 4 + i n 1 2 0 p d 1 1 9 ? o u t 1 09209-002 figure 2. 0 1 10 100 10 100 1k 10k 100k 1m 10m 100m v n (nv/ hz) frequency (hz) 09209-003 figure 3. voltage noise spectral density the low dc offset and excellent dynamic performance of the ada4930-1/ada4930-2 make them well suited for a wide variety of data acquisition and signal processing applications. the ada4930-1 is available in a pb-free, 3 mm 3 mm 16-lead lfcsp, and the ada4930-2 is available in a pb-free, 4 mm 4 mm 24-lead lfcsp. the pinout has been optimized to facilitate printed circuit board (pcb) layout and minimize distortion. the ada4930-1 is specified to operate over the ?40c to +105c temperature range, and the ada4930-2 is specified to operate over the ?40c to +105c temperature range for 3.3 v or 5 v supply voltages.
ada4930-1/ada4930-2 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 3.3 v operation ............................................................................ 3 3.3 v v ocm to v o, cm performance ............................................... 4 3.3 v general performance ......................................................... 4 5 v operation ............................................................................... 5 5 v v ocm to v o, cm performance .................................................. 6 5 v general performance ............................................................ 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 maximum power dissipation ..................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 test circuits ..................................................................................... 15 operational description ................................................................ 16 definition of terms .................................................................... 16 theory of operation ...................................................................... 17 analyzing an application circuit ............................................ 17 setting the closed-loop gain .................................................. 17 estimating the output noise voltage ...................................... 17 impact of mismatches in the feedback networks ................. 18 input common-mode voltage range ..................................... 18 minimum r g value .................................................................... 19 setting the output common-mode voltage .......................... 19 calculating the input impedance for an application circuit ....................................................................................................... 19 layout, grounding, and bypassing .............................................. 23 high performance adc driving ................................................. 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 10/10rev. 0 to rev. a changes to general description .................................................... 1 10/10revision 0: initial version
ada4930-1/ada4930-2 rev. a | page 3 of 28 specifications 3.3 v operation v s = 3.3 v, v icm = 0.9 v, v ocm = 0.9 v, r f = 301 , r g = 301 , r l, dm = 1 k, single-ended input, differential output, t a = 25c, t min to t max = ?40c to +105c, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit dynamic performance ?3 db small signal bandwidth v o, dm = 0.1 v p-p 1430 mhz ?3 db large signal bandwidth v o, dm = 2 v p-p 887 mhz bandwidth for 0.1 db flatness v o, dm = 0.1 v p-p ada4930-1 380 mhz ada4930-2 89 mhz slew rate v o, dm = 2 v step, 25% to 75% 2877 v/s settling time to 0.1% v o, dm = 2 v step, r l = 200 6.3 ns overdrive recovery time g = 3, v in, dm = 0.7 v p-p pulse 1.5 ns noise/harmonic performance hd2/hd3 v o, dm = 2 v p-p, f c = 10 mhz ?98/?97 db v o, dm = 2 v p-p, f c = 30 mhz ?91/?88 db v o, dm = 2 v p-p, f c = 70 mhz ?79/?79 db v o, dm = 2 v p-p, f c = 100 mhz ?73/?73 db third-order imd v o, dm = 1 v p-p/tone, f c = 70.05 mhz 0.05 mhz 91 dbc v o, dm = 1 v p-p/tone, f c = 140.05 mhz 0.05 mhz 86 dbc input voltage noise f = 100 khz 1.15 nv/hz input current noise f = 100 khz 3 pa/hz crosstalk f = 100 mhz, ada4930-2, r l = 200 ?90 db dc performance input offset voltage v ip = v in = v ocm = 0 v, r l = open circuit ?3.1 ?0.5 +3.1 mv input offset voltage drift t min to t max 2.75 v/c input bias current ?36 ?24 ?16 a input bias current drift t min to t max ?0.05 a/ c input offset current ?1.8 +0.1 +1.8 a open-loop gain r f = r g = 10 k, v o = 0.5 v, r l = open circuit 64 db input characteristics input common-mode voltage range 0.3 1.2 v input resistance differential 150 k common mode 3 m input capacitance common mode 1 pf cmrr v icm = 0.5 v dc; r f = r g = 10 k, r l = open circuit ?82 ?77 db output characteristics output voltage each single-ended output; r f = r g = 10 k 0.11 1.74 v linear output current each single-ended output; f = 1 mhz, tdh 60 dbc 30 ma output balance error f = 1 mhz 55 db
ada4930-1/ada4930-2 rev. a | page 4 of 28 3.3 v v ocm to v o, cm performance table 2. parameter test conditions/comments min typ max unit v ocm dynamic performance ?3 db bandwidth v o, cm = 0.1 v p-p 745 mhz slew rate v o, cm = 2 v p-p, 25% to 75% 828 v/s v ocm input characteristics input voltage range 0.8 1.1 v input resistance 7.0 8.3 10.3 k input offset voltage v os, cm = v o, cm ? v ocm ; v ip = v in = v ocm = 0 v ?25 +15.4 +31 mv input voltage noise f = 100 khz 23.5 nv/hz gain 0.99 1 1.02 v/v cmrr v ocm = 0.5 v dc; r f = r g = 10 k, r l = open circuit ?83 ?77 db 3.3 v general performance table 3. parameter test conditions/comments min typ max unit power supply operating range 3.3 v quiescent current per amplifier enabled 32 35 40 ma enabled, t min to t max variation 81 a/ c disabled 0.44 1.8 2.35 ma +psrr v icm = 0.5 v; r f = r g = 10 k, r l = open circuit ?74 ?70 db ?psrr v icm = 0.5 v; r f = r g = 10 k, r l = open circuit ?87 ?76 db power-down ( pd ) pd input voltage disabled <0.8 v enabled >1.3 v turn-off time 1 s turn-on time 12 ns pd pin bias current enabled pd = 3.3 v 0.09 a disabled pd = 0 v 97 a operating temperature range ?40 +105 c
ada4930-1/ada4930-2 rev. a | page 5 of 28 5 v operation v s = 5 v, v icm = 0.9 v, v ocm = 0.9 v, r f = 301 , r g = 301 , r l, dm = 1 k, single-ended input, differential output, t a = 25c, t min to t max = ?40c to +105c, unless otherwise noted. table 4. parameter test conditions/comments min typ max unit dynamic performance ?3 db small signal bandwidth v o, dm = 0.1 v p-p 1350 mhz ?3 db large signal bandwidth v o, dm = 2 v p-p 937 mhz bandwidth for 0.1 db flatness v o, dm = 0.1 v p-p ada4930-1 369 mhz ada4930-2 90 mhz slew rate v o, dm = 2 v step, 25% to 75% 3400 v/s settling time to 0.1% v o, dm = 2 v step, r l = 200 6 ns overdrive recovery time g = 3, v in, dm = 0.7 v p-p pulse 1.5 ns noise/harmonic performance hd2/hd3 v o, dm = 2 v p-p, f c = 10 mhz ?104/?101 db v o, dm = 2 v p-p, f c = 30 mhz ?91/?93 db v o, dm = 2 v p-p, f c = 70 mhz ?79/?82 db v o, dm = 2 v p-p, f c = 100 mhz ?73/?75 db third-order imd v o, dm = 1 v p-p/tone, f c = 70.05 mhz 0.05 mhz 94 dbc v o, dm = 1 v p-p/tone, f c = 140.05 mhz 0.05 mhz 90 dbc input voltage noise f = 100 khz 1.2 nv/hz input current noise f = 100 khz 2.8 pa/hz crosstalk f = 100 mhz, ada4930-2, r l = 200 ?90 db dc performance input offset voltage v ip = v in = v ocm = 0 v, r l = open circuit ?3.1 ?0.15 +3.1 mv input offset voltage drift t min to t max 1.8 v/c input bias current ?34 ?23 ?15 a input bias current drift t min to t max ?0.05 a/ c input offset current ?0.82 +0.1 +0.82 a open-loop gain r f = r g = 10 k, v o = 1 v, r l = open circuit 64 db input characteristics input common-mode voltage range 0.3 2.8 v input resistance differential 150 k common mode 3 m input capacitance common mode 1 pf cmrr v icm = 1 v dc; r f = r g = 10 k, r l = open circuit ?82 ?77 db output characteristics output voltage each single-ended output; r f = r g = 10 k 0.18 3.38 v linear output current each single-ended output; f = 1 mhz, tdh 60 dbc 30 ma output balance error f = 1 mhz 55 db
ada4930-1/ada4930-2 rev. a | page 6 of 28 5 v v ocm to v o, cm performance table 5. parameter test conditions/comments min typ max unit v ocm dynamic performance ?3 db bandwidth v o, cm = 0.1 v p-p 740 mhz slew rate v o, cm = 2 v p-p, 25% to 75% 1224 v/s v ocm input characteristics input voltage range 0.5 2.3 v input resistance 7.0 8.3 10.2 k input offset voltage v os, cm = v o, cm ? v ocm ; v ip = v in = v ocm = 0 v ?25 +0.35 +15 mv input voltage noise f = 100 khz 23.5 nv/hz gain 0.99 1 1.02 v/v cmrr v ocm = 1.5 v; r f = r g = 10 k, r l = open circuit ?80 ?77 db 5 v general performance table 6. parameter test conditions/comments min typ max unit power supply operating range 5 v quiescent current per amplifier enabled 31.1 34 38.4 ma enabled, t min to t max variation 74.5 a/ c disabled 0.45 1.8 2.6 ma +psrr v icm = 1 v; r f = r g = 10 k, r l = open circuit ?74 ?71 db ?psrr v icm = 1 v; r f = r g = 10 k, r l = open circuit ?91 ?75 db power-down ( pd ) pd input voltage disabled <2.5 v enabled >3 v turn-off time 1 s turn-on time 12 ns pd pin bias current enabled pd = 5 v 0.09 a disabled pd = 0 v 97 a operating temperature range ?40 +105 c
ada4930-1/ada4930-2 rev. a | page 7 of 28 absolute maximum ratings the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. rms voltages and currents must be used in these calculations. table 7. parameter rating supply voltage 5.5 v power dissipation see figure 4 storage temperature range ?65c to +125c operating temperature range ?40c to +105c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power planes reduces ja . figure 4 shows the maximum safe power dissipation vs. the ambient temperature for the ada4930-1 single 16-lead lfcsp (98c/w) and the ada4930-2 du al 24-lead lfcsp (67c/w) on a jedec standard 4-layer board. thermal resistance ja is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in eia/jesd51-7. 3.5 0 ?40 110 90 100 maximum power dissipation (w) temperature (c) 0.5 1.0 1.5 2.0 2.5 3.0 ?30?20?100 1020304050607080 ada4930-2 ada4930-1 09209-004 table 8. thermal resistance package type ja unit 16-lead lfcsp (exposed pad) 98 c/w 24-lead lfcsp (exposed pad) 67 c/w maximum power dissipation the maximum safe power dissipation in the ada4930-1/ada4930-2 packages is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ada4930-1/ada4930-2. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. figure 4. maximum power dissipation vs. ambient temperature, 4-layer board esd caution
ada4930-1/ada4930-2 rev. a | page 8 of 28 pin configurations and function descriptions notes 1. exposed paddle. the exposed pad is not electrically connected to the device. it is typically soldered to ground or a power plane on the pcb that is thermally conductive. 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 pd 10 +out 9v ocm 5 + v s 6 + v s 7 + v s 8 + v s 1 5 ? v s 1 6 ? v s 1 4 ? v s 1 3 ? v s ada4930-1 top view (not to scale) pin 1 indicator 09209-005 figure 5. ada4930-1 pin configuration pin 1 indicator 1 2 3 4 5 6 15 16 17 18 14 13 7 8 9 1 1 1 2 1 0 2 1 2 2 2 3 2 4 + i n 1 2 0 1 9 top view (not to scale) ada4930-2 ?in1 +fb1 +v s1 +v s1 ?fb2 +in2 ?v s2 ?v s2 v ocm1 +out1 pd2 ?out2 ? i n 2 + f b 2 + v s 2 v o c m 2 + o u t 2 + v s 2 ? v s 1 ? v s 1 ? f b 1 p d 1 ? o u t 1 notes 1. exposed paddle. the exposed pad is not electrically connected to the device. it is typically soldered to ground or a power plane on the pcb that is thermally conductive. 0 9209-006 figure 6. ada4930-2 pin configuration table 9. ada4930-1 pin function descriptions pin no. mnemonic description 1 ?fb negative output for feedback component connection. 2 +in positive input summing node. 3 ?in negative input summing node. 4 +fb positive output for feedback component connection. 5 to 8 +v s positive supply voltage. 9 v ocm output common-mode voltage. 10 +out positive output for load connection. 11 ?out negative output for load connection. 12 pd power-down pin. 13 to 16 ?v s negative supply voltage. epad exposed paddle. the exposed pad is not electrically connected to the device. it is typically soldered to ground or a power plane on the pcb that is thermally conductive. table 10. ada4930-2 pin function descriptions pin no. mnemonic description 1 ?in1 negative input summing node 1. 2 +fb1 positive output feedback pin 1. 3, 4 +v s1 positive supply voltage 1. 5 ?fb2 negative output feedback pin 2. 6 +in2 positive input summing node 2. 7 ?in2 negative input summing node 2. 8 +fb2 positive output feedback pin 2. 9, 10 +v s2 positive supply voltage 2. 11 v ocm2 output common-mode voltage 2. 12 +out2 positive output 2. 13 ?out2 negative output 2. 14 pd2 power-down pin 2. 15, 16 ?v s2 negative supply voltage 2. 17 v ocm1 output common-mode voltage 1. 18 +out1 positive output 1. 19 ?out1 negative output 1. 20 pd1 power-down pin 1. 21, 22 ?v s1 negative supply voltage 1. 23 ?fb1 negative output feedback pin 1. 24 +in1 positive input summing node 1. epad exposed paddle. the exposed pad is not electrically connected to the device. it is typically soldered to ground or a power plane on the pcb that is thermally conductive.
ada4930-1/ada4930-2 rev. a | page 9 of 28 typical performance characteristics t a = 25 c, v s = 5 v, v icm = 0.9 v, v ocm = 0.9 v, r l, dm = 1 k, unless otherwise noted. ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 1m 10m 100m 1g 10g frequency (hz) normalized closed loop gain (db) v in = 100mv g = 1, r g = 300 ? g = 2, r g = 150 ? g = 5, r g = 60 ? 0 9209-007 figure 7. small signal frequency response at gain = 1, gain = 2, and gain = 5 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 1m 10m 100m 1g 10g frequency (hz) closed loop gain (db) v in = 100mv v s = 3.3v v s = 5.0v 0 9209-008 figure 8. small signal frequency response at v s = 3.3 v and v s = 5 v ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 1m 10m 100m 1g 10g frequency (hz) closed loop gain (db) v in = 100mv t a = ?40c t a = +25c t a = +105c 0 9209-009 figure 9. small signal frequency response at t a = ?40c, t a = 25c, and t a = 105c ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 1m 10m 100m 1g 10g frequency (hz) normalized closed loop gain (db) v in = 2v p-p g = 1, r g = 300 ? g = 2, r g = 150 ? g = 5, r g = 60 ? 0 9209-010 figure 10. large signal frequency response at gain = 1, gain = 2, and gain = 5 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 3 0 6 1m 10m 100m 1g 10g frequency (hz) closed loop gain (db) v in = 2v p-p v s = 3.3v v s = 5.0v 0 9209-011 figure 11. large signal frequency response at v s = 3.3 v and v s = 5 v ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 3 0 6 1m 10m 100m 1g 10g frequency (hz) closed loop gain (db) v in = 2v p-p t a = ?40c t a = +25c t a = +105c 0 9209-012 figure 12. large signal frequency response at t a = ?40c, t a = 25c, and t a = 105c
ada4930-1/ada4930-2 rev. a | page 10 of 28 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 1m 10m 100m 1g 10g frequency (hz) normalized closed loop gain (db) v in = 100mv p-p r l = 1k ? r l = 200 ? 0 9209-013 figure 13. small signal frequency response for r l = 200 and r l = 1 k ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 1m 10m 100m 1g frequency (hz) gain (db) 09209-014 v in = 100mv figure 14. v ocm small signal frequency response ?120 ?110 ?100 ?90 ?80 ?70 distortion (dbc) ?60 ?50 ? 40 1m 10m 100m 200m frequency (hz) hd2, gain = 1 hd3, gain = 1 hd2, gain = 2 hd3, gain = 2 hd2, gain = 5 hd3, gain = 5 09209-015 figure 15. harmonic distortion vs. frequency for gain = 1, gain = 2, and gain = 5 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 3 0 6 1m 10m 100m 1g 10g frequency (hz) closed-loop gain (db) v in = 2v p-p r l = 1k ? r l = 200 ? 0 9209-016 figure 16. large signal frequency response for r l = 200 and r l = 1 k ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 1m 10m 100m 1g gain (db) frequency (hz) ada4930-2, 200 ? , out 1 ada4930-2, 200 ? , out 2 ada4930-1, 200 ? ada4930-1, 1k ? ada4930-2, 1k ? , out 1 ada4930-2, 1k ? , out 2 09209-017 figure 17. small signal 0.1 db flatness vs. frequency for r l = 200 and r l = 1 k ?110 ?100 ?90 ?80 ?70 ?60 ? 50 1m 10m 100m 200m distortion (dbc) frequency (hz) hd2, r l = 200 ? hd3, r l = 200 ? hd2, r l = 1k ? hd3, r l = 1k ? 09209-018 figure 18. harmonic distortion vs. frequency for r l = 200 and r l = 1 k
ada4930-1/ada4930-2 rev. a | page 11 of 28 ?110 ?100 ?90 ?80 ?70 ?105 ?95 ?85 ?75 ?65 ? 60 1m 10m 100m 200m distortion (dbc) frequency (hz) hd2, v s = 5.0v hd3, v s = 5.0v hd2, v s = 3.3v hd3, v s = 3.3v 09209-019 figure 19. ada4930-1 harmonic distortion vs. frequency at v s = 3.3 v and v s = 5 v ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 0.40.50.60.70.80.91.01.11.2 distortion (dbc) 70mhz, hd2 70mhz, hd3 10mhz, hd2 10mhz, hd3 v ocm above ? v s (v) 09209-020 figure 20. harmonic distortion vs. v ocm at v s = 3.3 v at 10 mhz and 70 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 distotion (dbc) frequency (hz) hd2, v out = 1v p-p hd3, v out = 1v p-p hd2, v out = 2v p-p hd3, v out = 2v p-p 1m 10m 100m 200m 09209-021 figure 21. distortion vs. v out at v s = 3.3 v ?140 ?120 ?100 ?80 ?60 ?40 ? 20 1.0 1.5 2.0 2.5 3.0 3.5 distorton (dbc) v out (v p-p) hd2, 3.3v hd3, 3.3v hd2, 5.0v hd3, 5.0v 09209-022 figure 22. harmonic distortion vs. output @ 10 mhz ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 0.5 1.0 1.5 2.0 2.5 3.0 distortion (dbc) v ocm above ? v s (v) 70mhz, hd2 70mhz, hd3 10mhz, hd2 10mhz, hd3 09209-023 figure 23. harmonic distortion vs. v ocm at 10 mhz and 70 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 69.8 69.9 70.0 70.1 70.2 70.3 frequency (mhz) normalized spectrum (dbc) 0 9209-024 figure 24. 70 mhz intermodulation distortion
ada4930-1/ada4930-2 rev. a | page 12 of 28 100k 1m 10m 100m 1g frequency (hz) cmrr (db) 09209-025 ?70 ?75 ?65 ?60 ?55 ?50 ?45 ? 40 figure 25. cmrr vs. frequency, r l = 200 ?140 1m 10m 100m 1g frequency (hz) crosstalk (db) ?120 ?100 ?80 ? 60 ?130 ?110 ?90 ?70 channel 1 to channel 2 channel 2 to channel 1 0 9209-026 figure 26. crosstalk vs. frequency, r l = 200 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1m 10m 100m 1g 10g frequency (hz) s parameters (db) s11 s22 0 9209-027 figure 27. s11, s22, r l = 200 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 100k 1m 10m 100m 1g psrr (db) frequency (hz) 09209-028 figure 28. psrr vs. frequency, r l = 200 1m 10m 100m 1g frequency (hz) crosstalk (db) ?50 ?35 ?55 ?40 ?25 ?60 ?45 ?30 ? 20 v in = 1v p-p gain = 2 0 9209-029 figure 29. output bala nce vs. frequency, r l = 200 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 1m 10m 100m 200m distortion (dbc) frequency (hz) r l = 200 ? r l = 1k ? 09209-030 figure 30. sfdr
ada4930-1/ada4930-2 rev. a | page 13 of 28 ?300 ?240 ?180 ?120 ?60 0 60 ?270 ?210 ?150 ?90 30 30 ?40 ?20 0 20 40 60 80 ?30 ?10 10 30 50 70 10k 100k 1m 10m 100m 1g 10g phase () gain (db) frequency (mhz) 09209-031 gain phase figure 31. open loop gain and phase 0.10 0.05 0 ?0.05 ?0.10 0246 1 v out (v) time (ns) 0 8 09209-032 figure 32. small signal pulse response 0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 246 1 v out (v) time (ns) 0 8 v o = 2v p-p v o = 1v p-p 09209-033 figure 33. large signal pulse response 0 1 10 100 10 100 1k 10k 100k 1m 10m 100m v n (nv/ hz) frequency (hz) 09209-034 figure 34. voltage noise spectral density 0.80 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 1.00 02468101214161820 v out (v) time (ns) 09209-035 figure 35. small signal v ocm pulse response 0 0.5 1.0 1.5 2.0 2.5 3.0 02468101214161820 v out (v) time (ns) 09209-036 figure 36. large signal v ocm pulse response
ada4930-1/ada4930-2 rev. a | page 14 of 28 ?0.25 0 0 100 200 300 400 500 600 700 800 900 1000 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 vol t age (v) time (ns) pd +out ?out 0 9209-037 figure 37. pd response vs. time ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 30 35 40 45 50 voltage (v) time (ns) v in 3 v o, dm 09209-038 figure 38. v o, dm overdrive recovery
ada4930-1/ada4930-2 rev. a | page 15 of 28 test circuits ada4930 1k ? +v s 301? 301? 50 ? 0.9v 0.9v 0.9v 301 ? 26.7 ? 301 ? v ocm 57.6 ? v in 09209-046 figure 39. equivalent basic test circuit +v s ada4930 301? 301? 50 ? 301? 50? 50? 26.7 ? 301? v ocm 57.6 ? v in 09209-047 0.9v 0.9v 0.9v figure 40. test circuit for output balance 0.9v 0.9v 0.9v 0.9v +v s ada4930 301? 301 ? 50? 301? 412? 412? 26.7 ? 301 ? v ocm 261? 57.6 ? v in filter 0.1f 0.1f filter 09209-048 figure 41. test circuit for distortion measurements
ada4930-1/ada4930-2 rev. a | page 16 of 28 operational description definition of terms +in ?in +out ?out +d in ? fb +fb ?d in v ocm r g r f r g v out, dm r l, dm r f ada4930 09209-049 figure 42. circuit definitions differential voltage differential voltage refers to the difference between two node voltages. for example, the output differential voltage (or, equivalently, output differential-mode voltage) is defined as v out, dm = ( v +out ? v ?out ) where v +out and v ?out refer to the voltages at the +out and ?out terminals with respect to a common reference. common-mode voltage common-mode voltage refers to the average of two node voltages. the output common-mode voltage is defined as v out, cm = ( v +out + v ?out )/2 balance output balance is a measure of how close the differential signals are to being equal in amplitude and opposite in phase. output balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider midpoint with the magnitude of the differential signal (see figure 39 ). by this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. dmout cmout v v error balance output , , =
ada4930-1/ada4930-2 rev. a | page 17 of 28 theory of operation the ada4930-1/ada4930-2 differ from conventional op amps in that they have two outputs whose voltages move in opposite directions and an additional input, v ocm . like an op amp, they rely on high open-loop gain and negative feedback to force these outputs to the desired voltages. the ada4930-1/ada4930-2 behave much like standard voltage feedback op amps and facilitate single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. like op amps, the ada4930-1/ada4930-2 have high input impedance and low output impedance. two feedback loops control the differential and common-mode output voltages. the differential feedback, set with external resistors, controls the differential output voltage. the common- mode feedback controls the common-mode output voltage. this architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. the output common-mode voltage is forced to be equal to the voltage applied to the v ocm input by the internal common-mode feedback loop. the internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. this results in differential outputs that are very close to the ideal of being identical in amplitude and are exactly 180?apart in phase. analyzing an application circuit the ada4930-1/ada4930-2 use high open-loop gain and negative feedback to force their differential and common-mode output voltages to minimize the differential and common-mode error voltages. the differential error voltage is defined as the voltage between the differential inputs labeled +in and ?in (see figure 42 ). for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common-mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these two assumptions, any application circuit can be analyzed. setting the closed-loop gain the differential-mode gain of the circuit in figure 42 is determined by g f dmin dmout r r v v = , , where the gain and feedback resistors, r g and r f , on each side are equal. estimating the output noise voltage the differential output noise of the ada4930-1/ada4930-2 can be estimated using the noise model in figure 43 . the input-referred noise voltage density, v nin , is modeled as differential. the noise currents, i nin? and i nin+ , appear between each input and ground. ada4930 + r f2 v nod v ncm v ocm v nin r f1 r g2 r g1 v nrf1 v nrf2 v nrg1 v nrg2 i nin+ i nin? 09209-050 figure 43. noise model similar to the case of conventional op amps, the output noise voltage densities can be estimated by multiplying the input- referred terms at +in and ?in by an appropriate output factor. the output voltage due to v nin is obtained by multiplying v nin by the noise gain, g n . the circuit noise gain is () 21 n | g + = 2 where the feedback factors are g1 f1 g1 1 rr r + = and g2 f2 g2 2 rr r + = . when the feedback factors are matched, r f1 /r g1 = r f2 /r g2 , 1 = 2 = , and the noise gain becomes g f n r r g +== 1 1 . the noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. the noise voltage density at the v ocm pin is v ncm . when the feedback networks have the same feedback factor, as in most cases, the output noise due to v ncm is common-mode and the output noise from v ocm is zero. each of the four resistors contributes (4ktr xx ) 1/2 . the noise from the feedback resistors appears directly at the output, and the noise from the gain resistors appears at the output multiplied by r f /r g . the total differential output noise density, v nod , is the root-sum- square of the individual output noise terms. = = 8 1i 2 )( nodi nod v v
ada4930-1/ada4930-2 rev. a | page 18 of 28 table 11. output noise voltag e density calculations for matched feedback networks input noise contribution input noise term input noise voltage density output multiplication factor differential output noise voltage density terms differential input v nin v nin g n v nod1 = g n (v nin ) inverting input i nin+ i nin+ (r f2 ) 1 v nod2 = (i nin+ )(r f2 ) noninverting input i nin? i nin? (r f1 ) 1 v nod3 = (i nin? )(r f1 ) v ocm input v ncm v ncm 0 v nod4 = 0 gain resistor r g1 v nrg1 (4ktr g1 ) 1/2 r f1 /r g1 v nod5 = (r f1 /r g1 )(4ktr g1 ) 1/2 gain resistor r g2 v nrg2 (4ktr g2 ) 1/2 r f2 /r g2 v nod6 = (r f2 /r g2 )(4ktr g2 ) 1/2 feedback resistor r f1 v nrf1 (4ktr f1 ) 1/2 1 v nod7 = (4ktr f1 ) 1/2 feedback resistor r f2 v nrf2 (4ktr f2 ) 1/2 1 v nod8 = (4ktr f2 ) 1/2 table 12. differential input, dc-coupled, v s = 5 v nominal gain (db) r f1 , r f2 () r g1 , r g2 () r in, dm () differential output noise density (nv/hz) 0 301 301 602 4.9 6 301 150 300 6.2 10 301 95.3 190.6 7.8 14 301 60.4 120.4 10.1 table 13. single-ended ground-referenced input, dc-coupled, r s = 50 , v s = 5 v nominal gain (db) r f1 , r f2 () r g1 () r t () r in, cm () r g2 () 1 differential output noise density (nv/hz) 0 301 142 64.2 190.67 170 5.9 6 301 63.4 84.5 95.06 95 7.8 10 301 33.2 1 k 53.54 69.3 9.3 14 301 10.2 1.15 k 17.5 57.7 10.4 1 r g2 = r g1 + (r s ||r t ). table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. table 12 and table 13 list several common gain settings, associated resistor values, input impedance, and output noise density for both balanced and unbalanced input configurations. impact of mismatches in the feedback networks as previously mentioned, even if the external feedback networks (r f /r g ) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. the amplitudes of the signals at each output remain equal and 180 out of phase. the input-to-output differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. the gain from the v ocm pin to v o, dm is equal to 2(1 ? 2)/(1 + 2) when 1 = 2, this term goes to zero and there is no differential output voltage due to the voltage on the v ocm input (including noise). the extreme case occurs when one loop is open and the other has 100% feedback; in this case, the gain from v ocm input to v o, dm is either +2 or ?2, depending on which loop is closed. the feedback loops are nominally matched to within 1% in most applications, and the output noise and offsets due to the v ocm input are negligible. if the loops are intentionally mismatched by a large amount, it is necessary to include the gain term from v ocm to v o, dm and account for the extra noise. for example, if 1 = 0.5 and 2 = 0.25, the gain from v ocm to v o, dm is 0.67. if the v ocm pin is set to 0.9 v, a differential offset voltage is present at the output of (0.9 v)(0.67) = 0.6 v. the differential output noise contribution is (5 nv/hz)(0.67) = 3.35 nv/hz. both of these results are undesirable in most applications; therefore, it is best to use nominally matched feedback factors. mismatched feedback networks also result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. as a practical summarization of the previous issues, resistors of 1% tolerance produce a worst-case input cmrr of approximately 40 db, a worst-case differential-mode output offset of 9 mv due to a 0.9 v v ocm input, negligible v ocm noise contribution, and no significant degradation in output balance error. input common-mode voltage range the input common-mode range at the summing nodes of the ada4930-1/ada4930-2 is specified as 0.3 v to 1.5 v at v s = 3.3 v. to avoid nonlinearities, the voltage swing at the +in and ?in terminals must be confined to these ranges.
ada4930-1/ada4930-2 rev. a | page 19 of 28 minimum r g value due to the wide bandwidth of the ada4930-1/ada4930-2, the value of r g must be greater than or equal to 301 at unity gain to provide sufficient damping in the amplifier front end. in the terminated case, r g includes the thevenin resistance of the source and load terminations. setting the output common-mode voltage the v ocm pin of the ada4930-1/ada4930-2 is biased at 3/10 of the total supply voltage above ?v s with an internal voltage divider. the input impedance of the v ocm pin is 8.4 k. when relying on the internal bias, the output common-mode voltage is within about 100 mv of the expected value. in cases where accurate control of the output common-mode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 . the output common-mode offset listed in the specifications section assumes that the v ocm input is driven by a low impedance voltage source. it is also possible to connect the v ocm input to a common-mode voltage (v cm ) output of an adc. however, care must be taken to ensure that the output has sufficient drive capability. the input impedance of the v ocm pin is approximately 10 k. if multiple ada4930-1/ada4930-2 devices share one reference output, it is recommended that a buffer be used. calculating the input impedance for an application circuit the effective input impedance depends on whether the signal source is single-ended or differential. for a balanced differential input signal, as shown in figure 44 , the input impedance (r in, dm ) between the inputs (+d in and ?d in ) is r in, dm = 2 r g . +v s ada4930 +in ?in r f r f +d in ?d in v ocm r g r g v out, dm 09209-051 figure 44. ada4930-1/ada4930-2 configured for balanced (differential) inputs for an unbalanced single-ended input signal, as shown in figure 45 , the input impedance is r in,se = r g1 )1( + + 21 21 where: 1 = f1 g1 g1 rr r + 2 = 2 2 f g2 g rr r + ada4930 r l v out, dm +v s ?v s r g1 r g2 r f2 r f1 v ocm r in, se 0 9209-052 figure 45. ada4930-1/ada4930-2 with unbalanced (single-ended) input for a balanced system where r g1 = r g2 = r g and r f1 = r f2 = r f , the equations simplify to ? ? ? ? ? ? ? ? ? ? ? ? + ? = + == )2( 1 f g f g in,se f g g rr r r rand rr r 21 the input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g1 . the common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider formed by r f2 and r g2 . this voltage is present at both input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across r g1 , partially bootstrapping it.
ada4930-1/ada4930-2 rev. a | page 20 of 28 4. set r f1 = r f2 = r f to maintain a balanced system. compensate the imbalance caused by r th . there are two methods available to compensate, which follow: te rminating a sing le-ended input this section describes the five steps that properly terminate a single-ended input to the ada4930-1/ada4930-2. assume a system gain of 1, r f1 = r f2 = 301 , an input source with an open- circuit output voltage of 2 v p-p, and a source resistance of 50 . figure 46 shows this circuit. ? add r th to r g2 to maintain balanced gain resistances and increase r f1 and r f2 to r f = th s v v gain(r g + r th ) to maintain the system gain. 1. calculate the input impedance. ? decrease r g2 to r g2 = gainv vr s th f to maintain system gain and decrease r g1 to (r g2 ? r th ) to maintain balanced gain resistances. 1 = 2 = 301/602 = 0.5 and r in = 401.333 r s 50? v s 2v p-p r in 401.333 ? ada4930 r l v out, dm +v s ?v s r g1 301 ? r g2 301 ? r f2 301? r f1 301? v ocm 09209-053 the first compensation method is used in the diff amp calculator ? tool. using the second compensation method, r g2 = 160.498 and r g1 = 160.498 ? 26.66 = 133.837 . the modified circuit is shown in figure 49 . ada4930 r l v out, dm +v s ?v s r th 26.661 ? r g1 133.837 ? r g2 160.498 ? r f2 301 ? r f1 301 ? v ocm v th 1.066v p-p 09209-056 figure 46. single-ended input impedance r in 2. add a termination resistor, r t . to match the 50 source resistance, r t is added. because r t ||401.33 = 50 , r t = 57.116 . ada4930 r l v out, dm +v s ?v s r s 50? r g1 301 ? r g2 301 ? r f2 301? r f1 301? v ocm v s 2v p-p r in 50? r t 57.116 ? 0 9209-054 figure 49. thevenin equivalent with matched gain resistors figure 49 presents an easily manageable circuit with matched feedback loops that can be easily evaluated. 5. the modified gain resistor, r g1 , changes the input impedance. repeat step 1 through step 4 several times using the modified value of r g1 from the previous iteration until the value of r t does not change from the previous iteration. after three additional iterations, the change in r g1 is less than 0.1%. the final circuit is shown in figure 50 with the closest 0.5% resistor values. figure 47. adding termination resistor r t 3. replace the source-termination resistor combination with its thevenin equivalent. the thevenin equivalent of the source resistance r s and the termination resistance r t is r th = r s ||r t = 26.66 . thethevenin equivalent of the source voltage is ada4930 r l v out, dm 1.990v p-p +v s ?v s r s 50 ? r g 142 ? v p v n r g2 169 ? r f1 301 ? r f2 301 ? v ocm v s 2v p-p 0.998v p-p r t 64.2 ? 09209-057 v th = v s t s t rr r + = 1.066 v p-p r s 50 ? v s 2 v p- p r t 57.116 ? r th 26.661 ? v th 1.066v p-p 0 9209-055 figure 48. thevenin equivalent circuit figure 50. terminated single-ende d-to-differential system with g = 1
ada4930-1/ada4930-2 rev. a | page 21 of 28 terminating a single-ended input in a single-supply applications when the application circuit of figure 50 is powered by a single supply, the common-mode voltage at the amplifier inputs, v p and v n , may have to be raised to comply with the specified input common-mode range. two methods are available: a dc bias on the source, as shown in figure 51 , or by connecting resistors r cm between each input and the supply, as shown on figure 54 . input common-mode adjustment with dc biased source to drive a 1.8 v adc with v cm = 1 v, a 3.3 v single supply minimizes the power dissipation of the ada4930-1/ada4930-2. the application circuit of figure 50 on a 3.3 v single supply with a dc bias added to the source is shown in figure 51 . ada4930 r l v out, dm 1.990v p-p 3.3v r s 50? r g1 142 ? v p v n r g2 142 ? r f2 301? r f1 301? v ocm v s 2v p-p v dc r t 64.2 ? 64.2 ? 50 ? 09209-151 figure 51. single-supply, te rminated single-ended-to-diffe rential system with g = 1 to determine the minimum required dc bias, the following steps must be taken: 1. convert the terminated inputs to their thevenin equivalents, as shown in the figure 52 circuit. ada4930 r l v out, dm 1.99v p-p 3.3v von vop r th 28.11 ? r g1 142 ? v p v n r g2 142 ? r f2 301? r f1 301? v ocm v th 1.124v p-p v dc-th 0 9209-159 r th 28.11 ? figure 52. thevenin equivalent of single-supply application circuit 2. wr ite a no dal e quat ion for v p or v n . () thdc th on thdc th p vvv vvv ? ? ?? ++ ++= 28.11142301 301 op thdc n v vv 28.11142301 301 ++ += ? re cognize that while the ada4930-1/ada4930-2 is in its linear operating region, v p and v n are equal. therefore, both equations in step 2 give equal results. 3. to comply with the minimum specified input common-mode voltage of 0.3 v at v s = 3.3 v, set the minimum value of v p and v n to 0.3 v. 4. recognize that v p and v n are at their minimum values when v op and v s are at their minimum (and therefore v on is at its maximum). let v p min = v n min = 0.3 v, v ocm = v cm = 1 v, v th min = ?v th /2 v on max = v ocm + v out, dm /4 and v op min = v ocm ? v out, dm /4 substitute conditions into the nodal equation for v p and solve for v dc-th . 0.3 = ?1.124/2 + v dc-th + 0.361 (1 + 1.99/4 = 1.124/2 C v dc-th ) 0.3 + 0.562 ? 0.361 ? 0.18 ? 0.203 = 0.639 v dc-th v dc-th = 0.186 v or substitute conditions into the nodal equation for v n and solve for v dc-th . 0.3 = v dc-th + 0.361 (1 ? 1.99/4 ? v dc-th ) 0.3 C 0.361 + 0.18 = 0.639 v dc-th v dc-th = 0.186 v 5. converting v dc-th from its thevenin equivalent results in v 0.330.186 = + = th th s dc r rr v the final application circuit is shown in figure 53 . the additional dc bias of 0.33 v at the inputs ensures that the minimum input common-mode requirements are met when the source signal is bipolar with a 2 v p-p amplitude and v ocm is at 1 v. 3.3v ada4930 r l v out, dm 1.990v p-p r s 50? r g1 142 ? r g2 142 ? r f2 301 ? r f1 301? v ocm v s 2v p-p r t 64.2 ? 64.2 ? 09209-160 v p v n 50 ? v dc 0.33v figure 53. single-supply applicat ion circuit with dc source bias
ada4930-1/ada4930-2 rev. a | page 22 of 28 input common-mode adjustment with resistors ca lculate the following: 1. 1 and 2. for the circuit shown in figure 54 , 1 = 0.5 and 2 = 0.5. the circuit shown in figure 54 shows an alternate method to bias the amplifier inputs, eliminating the dc source. 2. r cm for v p min = 0.3 v and v in min = ?0.5 v. r cm = 9933 . ada4930 r l v out, dm +v s ?v s 3.3v 3.3 v r s 50? r g1 301? r g2 301? r f2 301 ? r f1 301? r cm v ocm r cm v s v s v source 2v p-p r t 09209-152 v in 3. the new values for 1 and 2. 1 = 0.4925 and 2 = 0.4925. 4. the input impedance using the following: ?+ + = ? = ? 12 r r 21 21 r v v rr g1 f1 g1 inp p g1sein 1 1 r i n-se = 399.35 . 5. r t , r th , and v th . r t = 57.16 , r th = 26.67 , and v th = 1.067 v. 6. the new values for r g1 and r g2 . r g2 = 160.55 and r g1 = 133.88 . 7. the new values for 1 and 2. 1 = 0.284 and 2 = 0.317. figure 54. single-supply bias ing scheme with resistors 8. the new value of r cm . r cm = 4759.63 . define 1 = r p /r f1 and 2 = r n /r f2 , where r p = r g1 ||r cm ||r f1 and r n = r g2 ||r cm ||r f2 . 9. repeat step 3 through step 8 until the values of r g1 and r g2 remain constant between iterations. after four iterations, the final circuit is shown in figure 55 . set r f1 = r f2 = r f to maintain a balanced system, as shown. write a nodal equation at v p and solve for v p . ada4930 r l v out, dm +v s ?v s r s 50? r g1 142 ? r g2 170 ? r f2 301 ? r f1 301? r cm 1.87k ? r cm 1.87k ? v ocm + v s +v s v s 2v p-p r t 65.1 ? 09209-153 ++ + = cm f s ocm in g f p r r vvv r r 21 12 v 2 2 1 determine v p min . this is the minimum input common-mode voltage from the specifications section. for a 3.3 v supply, v p min = 0.3 v. determine the minimum input voltage, v in min at the output of the source. recognize that once properly terminated, the source voltage is ? of its open circuit value. therefore, v in min = ?0.5 v. rearrange the v p equation for r cm ? ? + = ocm minin g f p f s cm vv r r v 12 21 rvr 2 2 11 1 min figure 55. single-supply, single-ended input system with bias resistors
ada4930-1/ada4930-2 rev. a | page 23 of 28 layout, grounding, and bypassing the ada4930-1/ada4930-2 are high speed devices. realizing their superior performance requires attention to the details of high speed pcb design. the first requirement is to use a multilayer pcb with solid ground and power planes that cover as much of the board area as possible. bypass each power supply pin directly to a nearby ground plane, as close to the device as possible. use 0.1 f high frequency ceramic chip capacitors. provide low frequency bulk bypassing, using 10 f tantalum capacitors from each supply to ground. stray transmission line capacitance in combination with package parasitics can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking or possible oscillation. signal routing should be short and direct to avoid such parasitic effects. provide symmetrical layout for complementary signals to maximize balanced performance. 0 9209-058 figure 56. ada4930-1 ground and power plane voiding in the vicinity of r f and r g use radio frequency transmission lines to connect the driver and receiver to the amplifier. minimize stray capacitance at the input/output pins by clearing the underlying ground and low impedance planes near these pins (see figure 56 ). if the driver/receiver is more than one-eighth of the wavelength from the amplifier, the signal trace widths should be minimal. this nontransmission line configuration requires the underlying and adjacent ground and low impedance planes to be cleared near the signal lines. the exposed thermal paddle is internally connected to the ground pin of the amplifier. solder the paddle to the low impedance ground plane on the pcb to ensure the specified electrical performance and to provide thermal relief. to reduce thermal impedance further, it is recommended that the ground planes on all layers under the paddle be connected together with vias. 1.30 0.80 0.80 1.30 09209-059 figure 57. recommended pcb thermal attach pad dimensions (millimeters) 0.8 mm 1.3 mm power plane ground plane top metal bottom metal 09209-060 figure 58. cross-section of 4-layer pcb showing thermal via co nnection to buried ground plane (dimensions in millimeters)
ada4930-1/ada4930-2 rev. a | page 24 of 28 high performance adc driving the ada4930-1/ada4930-2 provide excellent performance in 3.3 v single-supply applications. the circuit shown in figure 59 is an example of the ada4930-1 driving an ad9255 , 14-bit, 80 msps adc that is specified to operate with a single 1.8 v supply. the performance of the adc is optimized when it is driven differentially, making the best use of the signal swing available within the 1.8 v supply. the ada4930-1 performs the single-ended-to-differential conversion, common- mode level shifting, and buffering of the driving signal. the ada4930-1 is configured for a single-ended input to differential output with a gain of 2 v/v. the 84.5 termination resistor, in parallel with the single-ended input impedance of 95.1 , provides a 50 termination for the source. the additional 31.6 (95 total) at the inverting input balances the parallel impedance of the 50 source and the termination resistor that drives the noninverting input. the v ocm pin is connected to the vcm output of the ad9255 and sets the output common mode of the ada4930-1 at 1 v. note that a dc bias must be added to the signal source and its thevenin equivalent to the gain resistor on the inverting side to ensure that the inputs of the ada4930-1 are kept at or above the specified minimum input common-mode voltage at all times. the 0.5 v dc bias at the signal source and the 0.314 v dc bias on the gain resistor at the inverting input set the inputs of the ada4930-1 to ~0.48 v dc. with 1 v p-p maximum signal swing at the input, the ada4930-1 inputs swing between 0.36 v and 0.6 v. for a common-mode voltage of 1 v, each ada4930-1 output swings between 0.501 v and 1.498 v, providing a 1.994 v p-p differential output. a third-order, 40 mhz, low-pass filter between the ada4930-1 and the ad9255 reduces the noise bandwidth of the amplifier and isolates the driver outputs from the adc inputs. the circuit shown in figure 60 is an example of ? of an ada4930-2 driving ? of an ad9640 , a 14-bit, 80 msps adc that is specified to operate with a single 1.8 v supply. the performance of the adc is optimized when it is driven differentially, making the best use of the signal swing available within the 1.8 v supply. the ada4930-2 performs the single- ended-to-differential conversion, common-mode level shifting, and buffering of the driving signal. the ada4930-2 is configured for a single-ended input to differential output with a gain of 2 v/v. the 88.5 termination resistor, in parallel with the single-ended input impedance of 114.75 , provides a 50 termination for the source. the increased gain resistance at the inverting input balances the 50 source resistance and the termination resistor that drives the noninverting input. the v ocm pin is connected to the cml output of the ad9640 and sets the output common mode of the ada4930-2 at 1 v. the 739 resistors between each input and the 3.3 v supply provide the necessary dc bias to guarantee compliance with the input common-mode range of the ada4930-2. for a common-mode voltage of 1 v, each ada4930-2 output swings between 0.501 v and 1.498 v, providing a 1.994 v p-p differential output. a third-order, 40 mhz, low-pass filter between the ada4930-2 and the ad9640 reduces the noise bandwidth of the amplifier and isolates the driver outputs from the adc inputs. 1.8v drvdd avdd vin? vin+ ad9255 agnd vcm d11 to d0 90pf 30pf 168nh 168nh 33? 33? 50 ? v in 1v p-p 95? 0.314v 63.4 ? v ocm 3.3v ada4930-1 + 0.5v 84.5 ? 301? 301? 09209-157 figure 59. driving an ad9255 , 14-bit, 80 msps adc 1.8v drvdd avdd vin? vin+ ad9640 agnd cml d11 to d0 90pf 30pf 168nh 168nh 50? v in 1v p-p 96.2 ? 64.2 ? 739 ? 739 ? v ocm v ocm 3.3v 3.3v 3.3v ada4930-2 + 88.5 ? 301 ? 301 ? 09209-158 figure 60. driving an ad9640 , 14-bit, 80 msps adc
ada4930-1/ada4930-2 rev. a | page 25 of 28 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. 072208-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 61. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-2) dimensions shown in millimeters compliant to jedec standards mo-220-vggd-8 08-18-2010-a 1 0.50 bsc p i n 1 i n d i c a t o r 2.50 bcs 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ seating plane coplanarity 0.05 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 0.20 min 2.44 2.34 sq 2.24 24 7 19 12 13 18 6 (bottom view) 0.60 max 0.60 max pin 1 indicator 4.10 4.00 sq 3.90 3.75 bsc sq exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 62. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-13) dimensions shown in millimeters ordering guide model 1 temperature range package description pack age option ordering quantity branding ada4930-1ycpz-r2 ?40c to +105c 16-lead lfcsp_vq cp-16-2 250 h1g ADA4930-1YCPZ-RL ?40c to +105c 16-lead lfcsp_vq cp-16-2 5,000 h1g ada4930-1ycpz-r7 ?40c to +105c 16-lead lfcsp_vq cp-16-2 1,500 h1g ada4930-1ycp-ebz evaluation board ada4930-2ycpz-r2 ?40c to +105c 24-lead lfcsp_vq cp-24-13 250 ada4930-2ycpz-rl ?40c to +105c 24-lead lfcsp_vq cp-24-13 5,000 ada4930-2ycpz-r7 ?40c to +105c 24-lead lfcsp_vq cp-24-13 1,500 ada4930-2ycp-ebz evaluation board 1 z = rohs compliant part.
ada4930-1/ada4930-2 rev. a | page 26 of 28 notes
ada4930-1/ada4930-2 rev. a | page 27 of 28 notes
ada4930-1/ada4930-2 rev. a | page 28 of 28 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09209-0-10/10(a)

▲Up To Search▲

Price & Availability of ADA4930-1YCPZ-RL

	To Download ADA4930-1YCPZ-RL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .